1. Technical Field
The present invention relates to impedance control in semiconductor devices and, more particularly, to an impedance controllable output drive circuit and an impedance control method, which is capable of checking a process, voltage and temperature (PVT) variation and automatically performing an impedance matching.
2. Discussion of Related Art
A semiconductor device can include pins to transmit data from or to the outside, and a data output circuit functioning as a data output buffer and driver circuit to provide internal data to the outside. The pins can be connected to transmission lines such as printed wiring provided on a mounting substrate in the semiconductor device incorporated into an electrical appliance. The pins can charge or discharge a floating capacitance or load capacitance (parasitic capacitance) existing on the mounting substrate. In an output drive circuit, output impedance ZQ can be controlled to match the output impedance with the transmission line to minimize distortion in the output signal caused by impedance mismatch.
When semiconductor devices are operated at higher speeds, the signal pulse width decreases, the influence of external noise increases, and the reflection of an output signal from an impedance mismatch in an interface terminal becomes a concern. Thus, a programmable impedance control scheme is employed to perform an input/output impedance matching. An example of a programmable impedance control (PIC) is disclosed in U.S. Pat. No. 6,307,424.
Another impedance control method is by use of a high speed transceiver logic (HSTL) interface, wherein one extra pin is used to control a desired output impedance value within a tolerance of about dozens of ohms. In such a scheme, it is often difficult to obtain a precise output impedance value due to changes in operating parameters such as power source voltage, operating temperature and manufacturing process.
U.S. Pat. No. 6,466,487 discloses in FIGS. 1a and 1b a programmable impedance control circuit, which includes an impedance update based on PVT variations, i.e., when a PVT variation is detected through a ZQ pad, up/down counting data is generated by counters 224 and 225. An update controller 52 receiving the counting data through registers 51 and 53 of FIG. 1b transmits control code data for an impedance update to an output drive circuit 1. In performing the impedance control by transmitting digitally coded control code data as described above, a change in the digitally coded control code data momentarily causes an impedance mismatch and may have an undesirable influence upon the data transmission.
FIG. 2 is a block diagram of a conventional impedance controllable output drive circuit. The circuit of FIG. 2 includes pull-up units 10-14 and pull-down units 20-24 corresponding to a pull-up transistor group 1a and a pull-down transistor group 1b within an output buffer 1 as in FIG. 1b, and an output pad 30 corresponding to the input/output pad 20 of FIG. 1B.
FIG. 2 illustrates a block configuration of an impedance controlled output driver, wherein a plurality of pull-up units 10-14 and a plurality of pull-down units 20-24 are connected commonly to the output pad 30. Pull-up control code data P[0:n] control impedance of pull-up units 10-14, and pull-down control code data N[0:n] control impedance of pull-down units 20-24. The pull-up control code data P[0:n] and pull-down control code data N[0:n] are changed from a high logic level to a low logic level, or from a low logic level to a high logic level, in conformity with a PVT variation, and are allocated to the corresponding pull-up units 10-14 and pull-down units 20-24. Thus, the number of activated transistor arrays of the pull-up units 10-14 and pull-down units 20-24 is controlled to update the impedance.
A control code to control the pull-up and pull-down impedances depends upon a value of internal data DinB, and performs an update for one of the pull-up and pull-down units. For example, when the internal data DinB is ‘1’ or ‘high’ logic level, output data represented on the output pad 30 is output as a value of ‘0’ or ‘low’ logic level. Thus a pull-down control code is not updated, but a pull-up control code is updated. On the contrary, when the internal data DinB is ‘0’, an output data is ‘1’, thus a pull-down impedance code is updated.
FIG. 3 is a circuit diagram illustrating an example of the configuration of pull-up and pull-down units shown in FIG. 2. For example, FIG. 3 illustrates a detailed configuration of one pull-up unit 10a and one pull-down unit 20a. With reference to FIG. 3, the pull-up unit 10a includes a pass transistor P1, a latch L1 constructed of two inverters IN2 and IN3, a NOR gate NOR1, an inverter IN4, a P-type metal oxide semiconductor (MOS) transistor PM1, and a resistance R1 connected to an output pad 30. The pull-down unit 20a includes a pass transistor P2, a latch L2 constructed of two inverters IN11 and IN12, a NAND gate NAN1, an inverter IN13, an N-type MOS transistor NM1, and a resistance R2 connected to the output pad 30.
In FIG. 3, when internal data DinB is ‘1’, the pass transistor P1 within the pull-up unit 10a is activated, and a correspondingly applied pull-up control code P_CODE is updated to the latch L1, and output data is output as ‘0’ by an activation of N-type MOS transistor NM1. When the internal data DinB is ‘0’, the pass transistor P2 within the pull-down unit 20a is activated, a pull-down control code N_CODE is updated to the latch L2, and output data is output as ‘1’ by an activation of P-type MOS transistor PM1.
The circuits of FIGS. 2 and 3 can experience difficulties when a pull-up code and a pull-down code are simultaneously updated during a time interval when data transition, or when an interim value of an abnormal code is transferred during a code transition. An undesired impedance may be provided momentarily, causing an output signal from the semiconductor device to be distorted or have noise. When a semiconductor device receives a distorted or noisy output signal, a set-up/hold failure or input logic level decision error may be caused.
In performing an impedance update in conformity with a PVT variation, it is desired to reduce an impedance matching error caused during a data transition. Also, a technique to perform an impedance update without a training sequence during a reset operation is desired.